Disruption of Automated Software Transfer

Disruption of Automated Software Transfer

Disruption of automated software transfer responds to hardware issues that do not match current software usage. This hardware event is called a trigger. 

Hardware event can be a busy transition to the external I / O device (such as UART input / output) or an internal event (such as a bus error, memory error, or periodic timer). If the hardware needs a service, which is typically busy with the configuration adjustment, it will ask for interruptions by setting its activation flag. The series is defined as a form of software action as it does. The performance of a service interruption is called the back cord. This series is caused by an application for hardware interference and is executed when the service interruption cycle returns from interruption (e.g., by signing up for BX LR). A new series is created for each disruption request. It is important to consider each application as a separate series because the local variables and registers used in the disruptive service system are different and different from one bug to another. 

In a multi-wire system, we view cables as a partnership to do all the work. Next we will develop ways for threads to connect (e.g., FIFO) and align with each other. Most embedded systems have the same overall goal. On the other hand, standard purpose computers can have many unrelated functions that need to be performed. The process is also described as a software act as it does. Processes do not work together to achieve the same shared goal. Fibers share access to I / O devices, system resources, and global flexibility, while processes have a wide range of global variables and system resources. Processes do not share I / O devices.

There are no standard definitions of the words mask, empowerment, and arm in professional societies, Computer Science, or Computer Engineering. However, in this section we will stick to the following specific definitions. Equipping the device means allowing the hardware trigger to interfere. Conversely, disconnecting the device means turning off or disconnecting the hardware trigger from interruption. Each potentially disruptive feature has a separate arm. A person sets a trigger if he is interested in a distraction from this source. Conversely, a person removes the detective weapons if he is not interested in the interference from this source. To enable means to allow for interruption at this time. In contrast, disabling means postponing the interruption until later. In the ARM Cortex-M processor there is a single interference that allows for a bit of a whole disruption process. Disable interruptions when it is not currently appropriate to accept interruptions. In particular, to disable interruptions we set the I bit to PRIMASK. In C, we allow and disable interruptions by calling the functions EnableInterrupts () and DisableInterrupts () respectively.

The software has flexible controls for some features of the disruption application sequence. First of all, each potential trigger has a separate arm software that you can use or disable. The software will set the arm parts of those devices where it wishes to receive interference, and will lock the arm pieces inside those devices where interference may be allowed. In other words it uses the armor to individually select which devices to request and which devices not to ask for interruptions. On most devices there is a small NVIC opening that must be set (SysTick interruptions from time to time are a different matter, without allowing NVIC). The third feature controlled by the software is to interrupt the bit. Specifically, 0 bit of special registry PRIMASK is a bit of masquerade mask, I. If this bit is 1 lot of distractions and exceptions are not allowed, we will describe it as disabled. If the bit is 0, then interruption is allowed, which we will define as approved. The fourth aspect is important. The BASEPRI register prevents distractions with less important distractions, but allows for more important distractions. For example if the software sets BASEPRI 3, applications with levels 0, 1, and 2 may interfere, while applications at levels 3 and higher will be postponed. The software can also determine the critical level of each disruption request. If BASEPRI is zero, the key feature is turned off and all interruptions are allowed. The fifth feature is the external hardware trigger. One example of a hardware trigger is the NVIC_ST_CTRL_R register counter that is periodically set by SysTick. Another example of computer triggers bits in the GPIO_PORTF_RIS_R register is set to the rising and falling edges of the digital input pins. 

Five conditions must be met for interference to be made:

1) device arm,
2) allow NVIC,
3) let the whole world,
4) The critical level of interference should be higher than the current level of performance, too
5) hardware event trigger.

In order for the disorder to occur, these five conditions must be true at the same time but can occur in any way.

Disruption results in a sequence of the following five events. 

First, the current command has expired. 

Second, the implementation of the current system is now suspended, with eight stack registers (R0, R1, R2, R3, R12, LR, PC, and PSR with R0 at the top) stamped. If the floating point unit in TM4C123 is active, an additional 18 words will be pushed into the stack representing the floating point position, making a total of 26 words. 

Third, the LR is set to a value indicator that the disruption cycle (ISR) is used (bits [31: 4] to 0xFFFFFFF, and bits [3: 0] specify the type of disruptive recovery to be performed). In our examples we will see LR set to 0xFFFFFFF9. If floating point registers are pushed, LR will be 0xFFFFFFE9. 

Fourth, the IPSR is based on the number of disturbances being considered. 

Finally, the PC is loaded with an ISR (vector) address.

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